The WM Computer Architectures Principles of Operation

Report
Author:Wulf, Wm, Department of Computer ScienceUniversity of Virginia
Abstract:

This report is a definition of, and partial rationale for. the WM family of computer architectures, ‘ins primary objective behind the WM design was concurrency - - concurrency at several levels. Since no single style of concurrency is suitable for all applications. several styles coexist and complement each other in the design. First, WM supports micro-concurrency at the instruction level; that is. it facilitates the execution of several scalar instructions concurrently. Second, WM supports vector processing; that is. it has single instructions that apply the same operation to a collection at data items. Finally, WM was designed to be a node in a multiprocessor, a "multi-computer", and facilities are provided for extremely low overhead communication and coordination among cooperating processors. A secondary, but important objective of WM was to permit a wider variety of implementations than is normally considered in machine designs. To this and, WM was designed as a "family oi architectures" parameterized by the size of the data manipulated by a family member. This approach permits members of the WM family to span the spectrum from 16-bit. integer only mini-computers through 64»bit supercomputers.
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Rights:
All rights reserved (no additional license for public reuse)
Language:
English
Source Citation:

Wulf, Wm. "The WM Computer Architectures Principles of Operation." University of Virginia Dept. of Computer Science Tech Report (1989).

Publisher:
University of Virginia, Department of Computer Science
Published Date:
1989