A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs

Report
Authors:Landon, T, Department of Computer ScienceUniversity of Virginia Salinas, M, Department of Computer ScienceUniversity of Virginia Klenke, R, Department of Computer ScienceUniversity of Virginia Aylor, J, Department of Computer ScienceUniversity of Virginia McKee, S, Department of Computer ScienceUniversity of Virginia Wright, K, Department of Computer ScienceUniversity of Virginia
Abstract:

This paper describes the design process used in developing a Stream Memory Controller (SMC)*. The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75mm process and has been tested at 36MHz.

Rights:
All rights reserved (no additional license for public reuse)
Language:
English
Source Citation:

Landon, T, M Salinas, R Klenke, J Aylor, S McKee, and K Wright. "A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs." University of Virginia Dept. of Computer Science Tech Report (1995).

Publisher:
University of Virginia, Department of Computer Science
Published Date:
1995