A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICsReport
This paper describes the design process used in developing a Stream Memory Controller (SMC)*. The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75mm process and has been tested at 36MHz.
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Landon, T, M Salinas, R Klenke, J Aylor, S McKee, and K Wright. "A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs." University of Virginia Dept. of Computer Science Tech Report (1995).
University of Virginia, Department of Computer Science