Evaluation of Dynamic Access Ordering Hardware

Report
Authors:McKee, S, Department of Computer ScienceUniversity of Virginia Oliver, C, Department of Computer ScienceUniversity of Virginia Wulf, Wm, Department of Computer ScienceUniversity of Virginia Wright, K, Department of Computer ScienceUniversity of Virginia Aylor, J, Department of Computer ScienceUniversity of Virginia
Abstract:

Memory bandwidth is rapidly becoming the limiting performance factor for many applica- tions, particularly for streaming computations - such as scientific vector processing or mul- timedia (de)compression - that lack the locality of reference that makes caching effective. We describe and evaluate a system that addresses the memory bandwidth problem for this class of computations by dynamically reordering stream accesses to exploit memory system architecture and device features. The technique is practical to implement, using existing compiler technology and requiring only a modest amount of special-purpose hardware. With our prototype system, we have observed performance improvements by over 200% over normal caching.

Rights:
All rights reserved (no additional license for public reuse)
Language:
English
Source Citation:

McKee, S, C Oliver, Wm Wulf, K Wright, and J Aylor. "Evaluation of Dynamic Access Ordering Hardware." University of Virginia Dept. of Computer Science Tech Report (1995).

Publisher:
University of Virginia, Department of Computer Science
Published Date:
1995