WM FIFOs: Size Analysis

Authors:Wulf, Wm, Department of Computer ScienceUniversity of Virginia Wad, Rohit, Department of Computer ScienceUniversity of Virginia

The WM computer architecture interposes data FIFOs between the execution units and memory. Data FIFOs improve performance by permitting memory delays to be overlapped with instruction execution. The depth of a FIFO depends on the average rate of memory accesses and the proximity of references to the FIFO. This project aims at exploring the effect of FIFO depth on performance, and suggesting a size that would be suitable for most applications.
Note: Abstract extracted from PDF file via OCR

All rights reserved (no additional license for public reuse)
Source Citation:

Wulf, Wm, and Rohit Wad. "WM FIFOs: Size Analysis." University of Virginia Dept. of Computer Science Tech Report (1991).

University of Virginia, Department of Computer Science
Published Date: