A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level

This paper presents research to address the temperature challenge in multicore processors through the lever of thermally-aware floorplanning. Specifically, it examines the thermal benefit in a variety of placement choices available in a multicore processor including alternative core orientation and insertion of L2 cache banks between cores as cooling buffers. In comparison with an idealized scheme that scatters the functional blocks of a multicore across the entire chip area to maximize uniformity, a combination of core orientation and L2 cache bank insertion achieves about 75% of the peak temperature reduction with negligible performance impact. On an average, the improvement in temperature is about 20% of the magnitude above the ambient temperature.

Sankaranarayanan, Karthik, Mircea Stan, and Kevin Skadron. "A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level." University of Virginia Dept. of Computer Science Tech Report (2009).