A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level

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Authors:Sankaranarayanan, Karthik, Department of Computer ScienceUniversity of Virginia Stan, Mircea, Department of Computer ScienceUniversity of Virginia Skadron, Kevin, Department of Computer ScienceUniversity of Virginia
Abstract:

This paper presents research to address the temperature challenge in multicore processors through the lever of thermally-aware floorplanning. Specifically, it examines the thermal benefit in a variety of placement choices available in a multicore processor including alternative core orientation and insertion of L2 cache banks between cores as cooling buffers. In comparison with an idealized scheme that scatters the functional blocks of a multicore across the entire chip area to maximize uniformity, a combination of core orientation and L2 cache bank insertion achieves about 75% of the peak temperature reduction with negligible performance impact. On an average, the improvement in temperature is about 20% of the magnitude above the ambient temperature.

Rights:
All rights reserved (no additional license for public reuse)
Language:
English
Source Citation:

Sankaranarayanan, Karthik, Mircea Stan, and Kevin Skadron. "A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level." University of Virginia Dept. of Computer Science Tech Report (2009).

Publisher:
University of Virginia, Department of Computer Science
Published Date:
2009