A Parallel VLSI Circuit Layout Methodology
ReportAuthors:Bapat, S, Department of Computer ScienceUniversity of Virginia Cohoon, J, Department of Computer ScienceUniversity of Virginia
Abstract:
We propose a parallel computation layout technique that solves the layout problem directly rather than decomposing it into the traditional distinct steps of placement and routing. The method combines a superior geometric partitioning algorithm with extensive use of pre~con1puted minimum - length Steiner trees to produce layouts.
Note: Abstract extracted from PDF file via OCR
Rights:
All rights reserved (no additional license for public reuse)
All rights reserved (no additional license for public reuse)
Language:
English
English
Source Citation:
Bapat, S, and J Cohoon. "A Parallel VLSI Circuit Layout Methodology." University of Virginia Dept. of Computer Science Tech Report (1992).
Publisher:
University of Virginia, Department of Computer Science
University of Virginia, Department of Computer Science
Published Date:
1992
1992
