A Parallel VLSI Circuit Layout MethodologyReport
We propose a parallel computation layout technique that solves the layout problem directly rather than decomposing it into the traditional distinct steps of placement and routing. The method combines a superior geometric partitioning algorithm with extensive use of pre~con1puted minimum - length Steiner trees to produce layouts.
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Bapat, S, and J Cohoon. "A Parallel VLSI Circuit Layout Methodology." University of Virginia Dept. of Computer Science Tech Report (1992).
University of Virginia, Department of Computer Science