Experimental Implementation of Dynamic Access OrderingReport
As microprocessor speeds increase, memory bandwidth is rapidly becoming the performance bottleneck in the execution of vector- like algorithms. Although caching provides adequate performance for many problems, caching alone is an insufficient solution for vector applications with poor temporal and spatial locality. More- over, the nature of memories themselves has changed. Current DRAM components should not be treated as uniform access-time RAM: achieving greater bandwidth requires exploiting the charactistics of components at every level of the memory hierarchy. This paper describes hardware-assisted access ordering and our hardware development effort to build a Stream Memory Controller (SMC) that implements the technique for a commercially available high-performance microprocessor, the Intel i860. Our strategy augments caching by combining compile-time detection of memory access patterns with a memory subsystem that decouples the order of requests generated by the processor from that issued to the memory system. This decoupling permits requests to be issued in an order that optimizes use of the memory system.
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McKee, S, R Klenke, A Schwab, Wm Wulf, S Moyer, C Hitchcock, and J Aylor. "Experimental Implementation of Dynamic Access Ordering." University of Virginia Dept. of Computer Science Tech Report (1993).
University of Virginia, Department of Computer Science