Interconnect Lifetime Prediction for Temperature-Aware Design

Authors:Lu, Zhijian, Department of Computer ScienceUniversity of Virginia Stan, Mircea, Department of Computer ScienceUniversity of Virginia Lach, John, Department of Computer ScienceUniversity of Virginia Skadron, Kevin, Department of Computer ScienceUniversity of Virginia

Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature-dependence of leakage power, circuit performance, IC package cost and reliability. Temperature-aware design tries to maximize performance under a given thermal envelope through various static and dynamic approaches. While existing interconnect reliability models assume a constant temperature, this paper presents a technique for probabilistically estimating interconnect lifetime for any time-varying temperature profile. With this formulation, interconnect lifetime can be modeled as a resource that is consumed over time, with the rate of consumption being a function of temperature. As a result, designers may be more aggressive in the temperature profiles that are allowed on a chip instead of using static worst-case assumptions. For example, performance (hence power and temperature) may be increased beyond what is allowed by worst-case restrictions for short periods as long as the increase is compensated for later by lower activity. With this model, temperature-aware designs will achieve higher overall performance while satisfying lifetime requirements.This report is superseded by TR CS-2004-08.
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Source Citation:

Lu, Zhijian, Mircea Stan, John Lach, and Kevin Skadron. "Interconnect Lifetime Prediction for Temperature-Aware Design." University of Virginia Dept. of Computer Science Tech Report (2003).

University of Virginia, Department of Computer Science
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