Design and Performance Analysis of Hardware Support for Parallel Simulations

Report
Authors:Reynolds, Jr, Department of Computer ScienceUniversity of Virginia Pancerella, Carmen, Department of Computer ScienceUniversity of Virginia Srinivasan, Sudhir, Department of Computer ScienceUniversity of Virginia
Abstract:

It has been established elsewhere [Reyn92] that hardware to support parallel discrete event simulations (PDES) is desirable. We describe the steps leading to the implementation of a hardware-based framework to support PDES. We begin with an exploration of the criteria necessary to make such a framework both practical and useful, concluding that maintenance of sequential consistency is sufficient, while "observable" sequential consistency is more desirable but difficult to attain. We derive a functional design based on these criteria, and from that derive a prototype design. Also, we establish the utility of our design, showing that computation of critical global values, such as global virtual time, can be done in times two orders of magnitude or better than typical event times in discrete event simulations.
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Rights:
All rights reserved (no additional license for public reuse)
Language:
English
Source Citation:

Reynolds, Jr, Carmen Pancerella, and Sudhir Srinivasan. "Design and Performance Analysis of Hardware Support for Parallel Simulations." University of Virginia Dept. of Computer Science Tech Report (1992).

Publisher:
University of Virginia, Department of Computer Science
Published Date:
1992