Data Cache Performance When Vector-Like Accesses Bypass the Cache

A Stream Memory Controller, when added to a conventional memory hierarchy, routes vector-like accesses around the data cache. A memory system was simulated under these conditions and the data cache performance increased dramatically. The gain in performance was a result of the increased temporal locality of the access pattern. The access pattern also showed a decrease in spatial locality, making smaller cache lines nearly as effective as long ones.

Nahas, Michael, and William Wulf. "Data Cache Performance When Vector-Like Accesses Bypass the Cache." University of Virginia Dept. of Computer Science Tech Report (1997).