Uniprocessor SMC Performance on Vectors with Non-Unit StridesReport
Memory bandwidth is rapidly becoming the performance bottleneck in the application of high performance microprocessors to vector-like algorithms, including the "grand challenge" scientific problems. Access ordering is one technique that can help bridge the processor-memory performance gap. Our solution combines compile-time detection of memory access patterns with a memory subsystem that decouples the order of requests generated by the processor from that issued to the memory system. This decoupling permits the requests to be issued in an order that optimizes use of the memory system. The hardware part of this solution is the Stream Memory Controller, or SMC. We have conducted numerous simulation experiments to evaluate uniprocessor SMC performance for unit-stride vectors; the results of these are presented elsewhere. Here we examine uniprocessor SMC performance for non-unit stride vectors. We present simulation results and extend the analytic performance model proposed in an earlier report.
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McKee, Sally. "Uniprocessor SMC Performance on Vectors with Non-Unit Strides." University of Virginia Dept. of Computer Science Tech Report (1993).
University of Virginia, Department of Computer Science